(A) Field of the Invention
The present invention relates to a programmable logic device in which optional combinational logic circuits can be realized by user programming, and more particularly to a programmable logic device in which useless storage elements are low in number, low power consumption can be achieved without complicating the circuits, and the number of input signals can be easily extended, whereby a multiple input logic circuit can be effectively realized.
(B) Description of the Prior Art
There has heretofore been known a programmable logic device (hereinafter referred to as "PLD") in which optional logic circuits can be realized by user programming.
FIGS. 8 and 9 are block diagrams showing the PLD of this type. In this PLD, a plurality of programmable logic elements (hereinafter referred to as "PLEs") 101 are provided on a chip 100. Further, input terminals 101a and output terminals 101b of the respective PLE 101 can be desirably connected to each other by programmable wiring means 102 (Refer to FIG. 8).
The PLE 101 is arranged by a logic circuit of a type using a programmable logic array (hereinafter referred to as "PLA") having programmable AND and OR planes, a logic circuit of a table lookup type using a memory, and so forth.
According to the above-described PLD, the user can desirably select functions of the respective PLEs 101 and the wiring means 102 between the PLEs 101, so that an optional large-sized circuit can be realized.
FIG. 10 is a circuit diagram of a synchronizing type full adder arranged by CMOS PLA by use of two-phase clocks .phi.1 and .phi.2 shown in FIG. 11. Seven product term lines 104 . . . in an AND plane 103 are formed such that programmable parallel switch elements 105 and 106 as shown in FIGS. 12 and 13 are connected to each other in series. Ends on one side of the product term lines 104 are input into an OR plane 108 through inverters 107 and connected to a circuit power source VDD through p channel MOS switch elements 109 to be ON-controlled when the clock .phi.1 is on the low level. Ends on the other side of the product term lines 104 are connected to a grounding GND of the circuit through n channel MOS switch elements 110 to be ON-controlled when the clock .phi.2 is on the high level. Signals including addition inputs X and Y and a carry-in signal Cin and outputs obtained by inverting these signals by inverters 111 ON-controls the parallel switch elements 105 of the aforesaid product term lines 104 when on the high level.
As shown in FIG. 13, in the parallel switch element 106, one 106a of the switch element is ON-programmed by a SRAM (Static Random Access Memory) cell 106b irrespective of the aforesaid signals and the inverted outputs thereof. On the contrary, the parallel switch element 105 is programmed such that a SRAM cell 105b to control one 105a of the switch element is turned off as shown in FIG. 12, so that the other 105c of the switch element can be controlled.
In the aforesaid OR plane 108, n channel MOS switch elements 112 to be ON-controlled by the high level outputs of the respective inverters 107 are parallelly connected to one another. Similarly to the above, ends on one side of the switch elements 112 are connected to the circuit power source VDD through switch elements 113 and connected to respective terminals of an addition output S and a carry-out output Cout through inverters 114. Ends of the other side of the switch elements 112 are connected to the grounding GND through switch elements 115.
FIG. 14 is a circuit diagram of a non-synchronizing type full adder formed by CMOS PLA. Both the AND plane 103 and OR plane 108 in this circuit are arranged in the same manner as in the circuit of the synchronizing type full adder as shown in FIG. 10. However, the former differs from the latter in that no clock is used, ends on one side of the product term lines 104 and the OR circuit (108) are directly connected to the grounding GND of the circuit, and ends on the other side connected to the inveters 107 and 114 are pulled up to the circuit power source VDD by resistors R100, R 101, R102, R103, R104, R105, R106, R107 and R108.
However, the PLD in the above-described prior art suffers from the following problems.
(1) When a table lookup type logic circuit having an input signal number N is used as the PLE, it is difficult to extend the input signal number. If a logic circuit corresponding to inputs of the number M (&gt;N) is programmed on this PLD for example, then very many PLEs are needed. Accordingly, the programmable logic circuit is subjected to many restrictions.
Needless to say the number of input signals of the above-described PLE can be set at M from the beginning. In that case, when the circuit having a small number of input signals is programmed, many unusable elements occur, so that the wastage is high.
Further, among the combinations of the input signals, there are many "Don't Care" inputs which don't affect any logic state. However, with the table lookup type logic circuit, all of the states of combinations should be stored, so that the programming efficiency is low.
(2) When the PLA is used as the PLE, useless storage elements are low in number and the product term lines can be connected to one another so that the number of input signals can be extended. However, with the non-synchronizing type PLA shown in FIG. 14, pull-up resistors R100-R108 are necessarily required, and it is difficult to lower the power consumption because of through currents between the circuit power source VDD.fwdarw. the grounding GND. Accordingly, from the viewpoint of the circuit scale, the scale cannot be made larger than a certain extent.
If a synchronizing type PLA as shown in FIG. 10 is used as a solution, the two-phase clocks .phi.1 and .phi.2 should be PG,6 used, whereby it becomes difficult for the user to handle. Further, due to the use of these clocks, it becomes necessary to provide a multiplicity of switch elements 109 and 110 for ON/OFF controlling the circuit, thereby presenting the problem of complicating the circuit.
If the technique of ATD (Address Transition Detection) is used, then DC power consumption can be reduced. However, in this case, difficulty is encountered in using the PLA in a larged-scaled PLD, because a complicated circuit is required.
Then, recently, there has been adopted a table lookup type logic circuit capable of being perfect CMOS arrangement in the large-scaled PLD.
In the large-scaled PLD, setting of the number of logic function inputs of the PLE serves as an important key to determine the degree of freedom of the PLD. That is, the more the number of inputs is, the easier the user can program optional circuit. However, when many inputs are set, it leads to an increase in a chip area of the PLD. Accordingly, it is desirable to adopt such a circuit arrangement that, first, the number of inputs into the PLE is set at a relatively low value, and, when the number of inputs into the circuit to be programmed by the user is large, the number of inputs may be easily increased.
However, with the table lookup type PLD, as shown in FIG. 15 for example, when the number of inputs is set at N (N=4 in an example shown in FIG. 15), memory 120 of 2.sup.N bits (in the example shown in FIG. 15, 16 bit RAM) are required. In a case of 8 inputs, a RAM of 256 bits is required. In FIG. 15, designated at 121 is an X-decoder for decoding input signals I1 and I2, and 122 a Y-decoder for decoding input signals I3 and I4.
In consequence, it is very difficult to cope with a multiplicity of inputs, and, in order to program logic functions having more logic signal inputs than the inputs into the PLE, it is necessary to connect a plurality of PLEs in series.
FIG. 16 shows an example in which a logic circuit having 24 inputs and 8 product term lines as shown is arranged by use of PLEs 130 for 4 inputs. However, in this example, since the extension is difficult, the interior of each broken line frame as shown should be supplied by one PLE, so that 11 PLEs are required in total. Furthermore, there have been presented the problems that, to connect a plurality of PLEs in series, the operating speed becomes slow and so on.